1. Field of the Invention
This invention relates in general to methods for measuring the frequency of periodic square pulse trains, and more particularly, to a method, for use on a parametric tester having a slow integration time and a slow delay time, to measure the output frequency of a ring oscillator through voltage sampling, which allows the output frequency of the ring oscillator to be more effectively and precisely measured.
2. Description of Related Art
A parametric tester is also referred as a wafer acceptance tester (WAT), which is basically composed of a probe station, a switch matrix, a voltage sourcing/measurement unit (SMU), and a computer means for control of the test programs and data acquisition. The parametric tester is widely used in semiconductor industry for the purpose of collecting lot-to-lot data that are used for statistical analysis on variations in the fabrication processes and performances of the fabricated semiconductor devices. The analysis can help engineers to optimize the design of process windows.
The parametric tester is also useful for measuring the output frequency of a ring oscillator which is fabricated on a semiconductor chip. The collected frequency data are related to the performance of the ring oscillator. One problem in the frequency measurements of ring oscillators is that the integration time and delay time are relatively lengthy, so as to make the measurement difficult to carry out.
FIG. 1 is a schematic block diagram of a system setup for a parametric tester (represented by a block indicated by the reference numeral 10) to measure the output frequency of a ring oscillator (represented by a block indicated by the reference numeral 102). The parametric tester 10 includes a switch matrix 108 and an SMU 110. The ring oscillator 102 is a closed loop circuit composed of a series of inverters (not shown) capable of generating a signal (which is typically a periodical square pulse train) having output frequency 103 in a range from several kilohertz to several megahertz. The waveform with the output frequency 103 can be visualized by using an oscilloscope. The exact value of the output frequency 103 is dependent on the characteristics of the transistors used to constitute the ring oscillator 102 on the semiconductor chip. The on-chip ring oscillator is a useful tool for the calibration of transistor mode in circuit designs.
The signal with output frequency 103 is first transferred to a buffer 104, and then to a frequency divider 106 that is capable of dividing the signal with output frequency 103 by a predetermined factor to obtain a reduced output frequency 107. The frequency divider 106 is composed of a plurality of D-type flip-flops (not shown). A 7-decade frequency divider can down convert a 5 MHz (period is 210.sup.-7 sec.) pulse train to a reduced frequency as low as 1 Hz.
The frequency-downconverted pulse train 107 is then transferred via the switch matrix 108 to the SMU 110 in the parametric tester 10. The SMU 110 then measures the frequency of the received pulse train.
One drawback to the foregoing parametric tester, however, is that, at the start of the sampling process on the received pulse train, there will be an initial delay time T.sub.d and subsequently an integration time T.sub.g (which is equal to one sampling period), and both are larger than the rising/falling transition time T.sub.r of the received pulse train. For instance, in a typical case, T.sub.d is 5 msec (millisecond) and T.sub.g is 50 msec, while T.sub.r is 10 .mu.sec (microsecond). Due to these two factors, even though the output frequency 103 from the ring oscillator 102 can be lowered by the frequency divider 106 to a reduced value of 1 Hz, it is nonetheless difficult for the parametric tester 10 to precisely measure the output frequency of the ring oscillator 102.